Technical Field
The present invention relates to the field of integrated circuit technologies, and in particular, to a carry-skip one-bit full adder and a field programmable gate array (FPGA) device.
Related Art
An FPGA is a logic device having rich hardware resources, a powerful parallel processing capability and flexible reconfigurability. With these features, the FPGA is widely applied in many fields such as data processing, communications, and networks.
Summation is the most common logical structure, and a main purpose of an internal arithmetical logic structure of the FPGA is to optimize the speed and implementation of summation. In the FPGA, an adder is usually implemented by using a carry chain. However, due to the architectural limitation of the FPGA, usually, a least-significant-bit carry of an n-bit full adder can be input only through a dedicated carry input end at the bottom of a logic element (LE), and therefore, a start position of a carry chain needs to be at the bottom of the LE, which significantly limits the layout.
In addition, if input and output ports of a full adder at any bit on a carry chain are occupied by another logical function, this carry chain will be interrupted. Therefore, when a logical function implemented on an FPGA chip is relatively complex, the number of available carry chains is extremely limited.